View MC9S08QE4_2974751.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor data sheet: technical data document number: mc9s08qe8 rev. 7, 4/2009 ? freescale semiconductor, inc., 2007-2009. all rights reserved. this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mc9s08qe8 32-pin lqfp case 873a 28-pin soic 751f-05 16-pin pdip 648 16-pin tssop 948f 20-pin soic 751d-07 features ? 8-bit hcs08 central processor unit (cpu) ? up to 20 mhz cpu at 3.6 v to 1.8 v across temperature range of ?40 c to 85 c ? hc08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources ?on-chip memory ? flash read/program/erase over full operating voltage and temperature ? random-access memory (ram) ? security circuitry to prevent unauthorized access to ram and flash contents ? power-saving modes ? two low power stop modes ? reduced power wait mode ? low power run and wait modes allow peripherals to run while voltage regulator is in standby ? peripheral clock gating register can disable clocks to unused modules, thereby reducing currents ? very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter ?6 s typical wake-up time from stop3 mode ? clock source options ? oscillator (xosc) ? loop-control pierce oscillat or; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz ? internal clock source (ics) ? internal clock source module containing a frequency-locked-loop (fll) controlled by internal or external reference; precisi on trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting bus freque ncies from 1 mhz to 10 mhz ? system protection ? watchdog computer operating prope rly (cop) reset with option to run from dedicated 1 khz intern al clock source or bus clock ? low-voltage warning with interrupt ? low-voltage detection with reset or interrupt ? illegal opcode detection with reset ? illegal address detection with reset ? flash block protection ? development support ? single-wire background debug interface ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) ? on-chip in-circuit emulator (ic e) debug module containing two comparators and nine trigger mode s; eight deep fifo for storing change-of-flow addresses and event-only data; debug module supports both tag and force breakpoints ? peripherals ? adc ? 10-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; 1.7 mv/ c temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 v to 1.8 v ? acmpx ? two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to tpm module; operation in stop3 ? sci ? full-duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wake-up on active edge ? spi ? full-duplex or si ngle-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting ? iic ? up to 100 kbps with maxi mum bus loading; multi-master operation; programmable slave address; interrupt driven byte-by-byte data transfer; supporting broadcast mode and 10-bit addressing ? tpmx ? two 3-channel (tpm1 and tpm2); selectable input capture, output compare, or buffered edge- or center-aligned pwm on each channel ? rtc ? (real-time counter) 8-bit modulus counter with binary or decimal based prescaler; external clock source for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 khz) for cyclic wakeup without external components; runs in all mcu modes ? input/output ? 26 gpios, one output-only pin and one input-only pin ? eight kbi interrupts with selectable polarity ? hysteresis and configurable pullup device on all input pins; configurable slew rate and dr ive strength on all output pins. ? package options ? 32-pin lqfp, 28-pin soic, 20-pin soic, 16-pin pdip, 16-pin tssop document number: mc9s08qe8 rev. 7, 4/2009 mc9s08qe8 series covers: mc9s08qe8 and MC9S08QE4 an energy efficient solution by freescale
mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 2 revision history to provide the most up-to-date information, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to ve rify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. rev date description of changes 2 nov 7 2007 initial preliminary product preview release. 3 jan 22 2008 initial public release. 4 march 13 200 8 added figure 11 . 5 october 8 2008 updated the stop2 a nd stop3 mode supply current in the ta b l e 8 . replaced the stop mode adders section from ta bl e 8 with an individual ta b l e 9 with new specifications. added a footnote to the min. of the suppply voltage in ta bl e 7 . changed the typical value of |i in | and |i oz | to ? (no typical value) in ta b l e 7 . added t vrr to ta b l e 1 2 . updated ?how to reach us? information. 6 nov. 4 2008 updated the operating voltage in ta bl e 7 . 7 april 29 2009 changed v ddad to v dda , i ddad to i dda , and v ssad to v ssa . in ta bl e 7 , added |i oztot |. in ta bl e 1 1 , updated the dco output frequency range-trimmed, and changed some symbols. updated typicals and max. for t irst. updated ta b l e 1 7 . related documentation find the most current versions of al l documents at: http ://www.freescale.com reference manual (mc9s08qe8rm) contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, cpu, and all module information. 1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 parameter classification. . . . . . . . . . . . . . . . . . . . 7 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . 8 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . 8 3.5 esd protection and latch-up immunity. . . . . . . 10 3.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 supply current characteristics. . . . . . . . . . . . . . 14 3.8 external oscillator (xoscvlp) characteristics . 17 3.9 internal clock source (ics) characteristics . . . . 18 3.10 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . 20 3.10.1control timing . . . . . . . . . . . . . . . . . . . . . 20 3.10.2tpm module timing. . . . . . . . . . . . . . . . . 21 3.10.3spi timing . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 analog comparator (acmp) electricals. . . . . . . 24 3.12 adc characteristics. . . . . . . . . . . . . . . . . . . . . . 25 3.13 flash specifications . . . . . . . . . . . . . . . . . . . . . . 29 3.14 emc performance . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.1conducted transient susceptibility . . . . . 30 4 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table of contents
mcu block diagram mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 3 1 mcu block diagram the block diagram, figure 1 , shows the structure of mc9s08qe8 series mcu. figure 1. mc9s08qe8 series block diagram iic module (iic) user flash user ram hcs08 core cpu bdc ptb7/scl/extal port b hcs08 system control resets and interrupts modes of operation power management cop lvd ptb6/sda/xtal ptb5/tpm1ch1/ss ptb4/tpm2ch1/miso ptb3/kbip7/mosi/adp7 ptb2/kbip6/spsck/adp6 voltage regulator port a pta1/kbip1/tpm2ch0/adp1/acmp1? analog comparator (acmp1) low-power oscillator 20 mhz internal clock source (ics) 31.25 khz to 38.4 khz 1 mhz to 16 mhz (xoscvlp) v ss v dd analog-to-digital converter (adc12) 12-bit ptb1/kbip5/txd/adp5 ptb0/kbip4/rxd/adp4 port c ptc7/acmp2? ptc6/acmp2+ ptc5/acmp2o ptc4 real-time counter (mc9s08qe8 = 8192 bytes) (MC9S08QE4 = 4096 bytes) (mc9s08qe8 = 512 bytes) (MC9S08QE4 = 256 bytes) pta3/kbip3/scl/adp3 pta2/kbip2/sda/adp2 pta0/kbip0/tpm1ch0/adp0/acmp1+ pta4/acmp1o/bkgd/ms pta5/irq/tclk/reset irq pins not availabl e on 16-pin packages pins not available on 16-pin or 20-pin packages (rtc) analog comparator (acmp2) pta7/tpm2ch2/adp9 pta6/tpm1ch2/adp8 ptc3 ptc2 ptc1/tpm2ch2 ptc0/tpm1ch2 port d ptd3 ptd2 ptd1 ptd0 v ssa /v refl v dda /v refh pins not available on 16-pin , 20-pin or 28-pin packages bkgd/ms irq extal xtal v refl v refh scl sda serial peripheral interface module (spi) miso mosi spsck ss interface module (sci) serial communications rxd txd debug module (dbg) tclk tpm2ch0 tpm2ch1 acmp1o acmp1? acmp1+ acmp2o acmp2? acmp2+ adp9?adp0 tpm2ch2 tclk tpm1ch0 tpm1ch1 tpm1ch2 16-bit timer pwm module (tpm1) 16-bit timer pwm module (tpm2) keyboard interrupt module (kbi) kbip7?kbip0 v ssa v dda v ssa v dda notes: when pta5 is configured as reset , pin becomes bi-directional with output being open-drain drive cont aining an internal pullup device. when pta4 is configured as bkgd, pin becomes bi-directional. for the 16-pin and 20-pin packages, v ssa /v refl and v dda /v refh are double bonded to v ss and v dd respectively.
mc9s08qe8 series data sheet, rev. 7 pin assignments freescale semiconductor 4 2 pin assignments this section shows the pin assignments for the mc9s08qe8 series devices. figure 2. mc9s08qe8 series in 32-pin lqfp package ptd3 v dda /v refh 1 2 3 4 5 6 7 8 v ssa /v refl v ss 19 18 17 10 11 12 13 14 15 9 24 32 16 252627 v dd 20 21 22 23 31 30 29 28 pta5/irq/tclk/reset pta4/acmp1o/bkgd/ms pta7/tpm2ch2/adp9 pta0/kbip0/tpm1ch0/adp0/acmp1+ ptc0/tpm1ch2 ptb3/kbip7/mosi/adp7 ptb2/kbip6/spsck/adp6 ptb1/kbip5/txd/adp5 ptb0/kbip4/rxd/adp4 pta2/kbip2/sda/adp2 pta3/kbip3/scl/adp3 pta1/kbip1/tpm2ch0adp1/acmp1? ptc1/tpm2ch2 ptc2 ptb4/tpm2ch1/miso ptc7/acmp2? ptb6/sda/xtal ptb5/tpm1ch1/ss ptc5/acmp2o ptc4 ptc3 ptd0 ptd1 ptb7/scl/extal ptd2 pta6/tpm1ch2/adp8 ptc6/acmp2+ pins shown in bold type are lost in the next lower pin count package.
pin assignments mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 5 figure 3. mc9s08qe8 series in 28-pin soic package figure 4. mc9s08qe8 series in 20-pin soic package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ptc0/tpm1ch2 ptb3/kbip7/mosi/adp7 ptb2/kbip6/spsck/adp6 ptb1/kbip5/txd/adp5 ptb0/kbip4/rxd/adp4 pta2/kbip2/sda/adp2 pta3/kbip3/scl/adp3 pta1/kbip1/tpm2ch0/adp1/acmp1? pta0/kbip0/tpm1ch0/adp0/acmp1+ pta7/tpm2ch2/adp9 pta6/tpm1ch2/adp8 ptb4/tpm2ch1/miso ptc3 pta5/irq/tclk/reset pta4/acmp1o/bkgd/ms v dd v ss ptb7/scl/extal ptb6/sda/xtal ptb5/tpm1ch1/ss ptc1/tpm2ch2 ptc6/acmp2+ ptc7/acmp2? ptc2 ptc4 ptc5/acmp2o v dda /v refh v ssa /v refl pins shown in bold type are lost in the next lower pin count package. 1 2 3 4 5 6 7 8 9 10 11 13 14 ptc2 ptb4/tpm2ch1/miso ptc3 ptc0/tpm1ch2 ptb3/kbip7/mosi/adp7 ptb2/kbip6/spsck/adp6 ptb1/kbip5/txd/adp5 ptb0/kbip4/rxd/adp4 pta2/kbip2/sda/adp2 pta3/kbip3/scl/adp3 pta1/kbip1/tpm2ch0/adp1/acmp1? pta0/kbip0/tpm1ch0/adp0/acmp1+ ptc1/tpm2ch2 pta5/irq/tclk/reset pta4/acmp1o/bkgd/ms v dd v ss ptb7/scl/extal ptb6/sda/xtal ptb5/tpm1ch1/ss 15 16 17 18 19 20 12 pins shown in bold type are lost in the next lower pin count package.
mc9s08qe8 series data sheet, rev. 7 pin assignments freescale semiconductor 6 figure 5. mc9s08qe8 series in 16-pin pdip and tssop packages table 1. pin availability by package pin-count pin number <-- lowest priority --> highest 32 28 20 16 port pin alt 1 alt 2 alt 3 alt 4 1 ???ptd1 2 ???ptd0 3533 v dd 46?? v dda /v refh 57?? v ssa /v refl 6844 v ss 7955ptb7 scl 1 extal 8106 6ptb6 sda 1 xtal 9 11 7 7 ptb5 tpm1ch1 ss 10 12 8 8 ptb4 tpm2ch1 miso 11 13 9 ? ptc3 12 14 10 ? ptc2 13 15 11 ? ptc1 tpm2ch2 2 14 16 12 ? ptc0 tpm1ch2 3 15 17 13 9 ptb3 kbip7 mosi adp7 16 18 14 10 ptb2 kbip6 spsck adp6 17 19 15 11 ptb1 kbip5 txd adp5 18 20 16 12 ptb0 kbip4 rxd adp4 19 21 ? ? pta7 tpm2ch2 2 adp9 20 22 ? ? pta6 tpm1ch2 3 adp8 21???ptd3 22???ptd2 23 23 17 13 pta3 kbip3 scl 1 adp3 24 24 18 14 pta2 kbip2 sda 1 adp2 25 25 19 15 pta1 kbip1 tpm2ch0 adp1 4 acmp1? 4 1 2 3 4 5 6 7 8 9 10 11 13 14 ptb4/tpm2ch1/miso ptb3/kbip7/mosi/adp7 ptb2/kbip6/spsck/adp6 ptb1/kbip5/txd/adp5 ptb0/kbip4/rxd/adp4 pta2/kbip2/sda/adp2 pta3/kbip3/scl/adp3 pta1/kbip1/tpm2ch0adp1/acmp1? pta0/kbip0/tpm1ch0/adp0/acmp1+ pta5/irq/tclk/reset pta4/acmp1o/bkgd/ms v dd v ss ptb7/scl/extal ptb6/sda/xtal ptb5/tpm1ch1/ss 15 16 12
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 7 3 electrical characteristics 3.1 introduction this section contains electrical a nd timing specifications for the mc9s 08qe8 series of microcontrollers available at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 26 26 20 16 pta0 kbip0 tpm1ch0 adp0 4 acmp1+ 4 27 27 ? ? ptc7 acmp2? 28 28 ? ? ptc6 acmp2+ 29 1 ? ? ptc5 acmp2o 30 2 ? ? ptc4 31 3 1 1 pta5 irq tclk reset 32 4 2 2 pta4 acmp1o bkgd ms 1 iic pins, scl and sda can be repositioned using iicps in sopt2, default reset locations are pta3 and pta2. 2 tpm2ch2 pin can be repositioned using tpm2ch2ps in sopt2, default reset location is pta7. 3 tpm1ch2 pin can be repositioned using tpm1ch2ps in sopt2, default reset location is pta6. 4 if adc and acmp1 are enabled, both modules will have access to the pin. table 2. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 1. pin availability by package pin-count (continued) pin number <-- lowest priority --> highest 32 28 20 16 port pin alt 1 alt 2 alt 3 alt 4
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 8 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table 3 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. 3.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the mcu design. to take p i/o into account in power calc ulations, determine the diff erence between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the diff erence between pin voltage and v ss or v dd will be very small. table 3. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to 3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins, except for pta5 are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?55 to 150 c
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 9 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . table 4. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 85 c maximum junction temperature t jm 95 c thermal resistance single-layer board 32-pin lqfp ja 66 c/w 28-pin soic 57 20-pin soic 71 16-pin pdip 64 16-pin tssop 108 thermal resistance four-layer board 32-pin lqfp ja 47 c/w 28-pin soic 42 20-pin soic 52 16-pin pdip 47 16-pin tssop 78
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 10 3.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling precautions must be taken to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. all esd testing is in conformity with aec-q100 stress test qual ification for automotive grade integrated circuits. during the device qualification, esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is perf ormed per the applicable device specification at room temperature fo llowed by hot temperature, unless in structed otherwise in the device specification. table 5. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 3 ? machine series resistance r1 0 storage capacitance c 200 pf number of pulses per pin ? 3 ? latch-up minimum input voltage limit ? ?2.5 v maximum input voltage limit ? 7.5 v table 6. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 machine model (mm) v mm 200 ? v 3 charge device model (cdm) v cdm 500 ? v 4 latch-up current at t a = 85 ci lat 100 ? ma
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 11 3.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 7. dc characteristics num c characteristic symbol condition min. typical 1 max. unit 1 operating voltage v dd rising v dd falling 2.0 2 1.8 3.6 v 2 c output high voltage all i/o pins, low-drive strength v oh v dd > 1.8 v, i load = ?2 ma v dd ? 0.5 ? ? v p all i/o pins, high-drive strength v dd > 2.7 v, i load = ?10 ma v dd ? 0.5 ? ? c v dd > 1.8v, i load = ?2 ma v dd ? 0.5 ? ? 3 d output high current max total i oh for all ports i oht ???1 0 0m a 4 c output low voltage all i/o pins, low-drive strength v ol v dd > 1.8 v, i load = 0.6 ma ??0.5 v p all i/o pins, high-drive strength v dd > 2.7 v, i load = 10 ma ??0.5 c v dd > 1.8 v, i load = 3 ma ??0.5 d output low current max total i ol for all ports i olt ???1 0 0m a 5 6 p input high voltage all digital inputs v ih v dd > 2.7 v 0.70 v dd ?? v cv dd > 1.8 v 0.85 v dd ?? 7 p input low voltage all digital inputs v il v dd > 2.7 v ? ? 0.35 v dd cv dd > 1.8 v ? ? 0.30 v dd 8c input hysteresis all digital inputs v hys ? 0.06 x v dd ??mv 9p input leakage current all input only pins (per pin) |i in |v in = v dd or v ss ?? 1 a 10 p hi-z (off-state) leakage current all input/output (per pin) |i oz |v in = v dd or v ss ?? 1 a 11 p to t a l leakage combined for all inputs and hi-z pins all input only and i/o |i oztot |v in = v dd or v ss ?? 2 a 12a p pullup, pulldown resistors all digital inputs, when enabled (all i/o pins other than pta5/irq/tclk/reset r pu, r pd 17.5 ? 52.5 k ?
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 12 12b c pullup, pulldown resistors (pta5/irq/tclk/reset ) r pu, r pd (note 3 ) 17.5 ? 52.5 k ? 13 c dc injection current 4, 5, 6 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma 14 c input capacitance, all pins c in ???8p f 15 c ram retention voltage v ram ??0 . 61 . 0v 16 c por re-arm voltage 7 v por ? 0.9 1.4 2.0 v 17 d por re-arm time t por ?1 0?? s p low-voltage detection threshold v lv d v dd falling v dd rising 1.80 1.88 1.84 1.92 1.88 1.96 v 18 p low-voltage warning threshold v lv w v dd falling v dd rising 2.08 2.14 2.24 v 19 p low-voltage inhibit reset/recover hysteresis v hys ??8 0?m v 20 21 p bandgap voltage reference 8 v bg ? 1.151.171.18v 1 typical values are measured at 25 c. characterized, not tested 2 as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above v lv d l . 3 the specified resistor value is the actual value internal to the device. the pullup or pulldown value may appear higher when measured externally on the pin. 4 all functional non-supply pins, except for pta5 are internally clamped to v ss and v dd . 5 input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current greater than maximum injection current. this will be the great est risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7 maximum is highest voltage that por is guaranteed. 8 factory trimmed at v dd = 3.0 v, temp = 25 c table 7. dc characteristics (continued) num c characteristic symbol condition min. typical 1 max. unit
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 13 figure 6. pullup and pulldown typical resistor values (v dd = 3.0 v) figure 7. typical low-side driver (sink) characteristics ? low drive (ptxdsn = 0) figure 8. typical low-side driver (sink) characteristics ? high drive (ptxdsn = 1) pullup resistor typicals v dd (v) pull-up resistor (k ) 20 25 30 35 40 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 25 c 85 c ?40 c pulldown resistor typicals v dd (v) pulldown resistance (k ) 20 25 30 35 40 1.8 2.3 2.8 3.3 25 c 85 c ?40 c 3.6 typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 typical v ol vs v dd v dd (v) v ol (v) 0 0.05 0.1 0.15 0.2 1234 25 c 85 c ?40 c 25 c, i ol = 2 ma 85 c, i ol = 2 ma ?40 c, i ol = 2 ma typical v ol vs i ol at v dd = 3.0 v i ol (ma) v ol (v) 0 0.2 0.4 0.6 0.8 1 0102030 typical v ol vs v dd v dd (v) v ol (v) 0 0.1 0.2 0.3 0.4 1234 i ol = 6 ma i ol = 3 ma i ol = 10 ma 25 c 85 c ?40 c 25 c 85 c ?40c
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 14 figure 9. typical high-side (source) characteristics ? low drive (ptxdsn = 0) figure 10. typical high-side (source) characteristics ? high drive (ptxdsn = 1) 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 8. supply current characteristics num c parameter symbol bus freq v dd (v) typical 1 max unit temp (c) 1 p run supply current fei mode, all modules on ri dd 10 mhz 3 5.60 8.2 ma ?40 to 85 c t1 m h z 0 . 8 0 ? 2 t run supply current fei mode, all modules off ri dd 10 mhz 3 3.60 ? ma ?40 to 85 c t1 m h z 0 . 5 1 ? 3 t run supply current lprs = 0, all modules off ri dd 16 khz fbilp 3 165 ? a ?40 to 85 c t 16 khz fbelp 105 ? 4 t run supply current lprs = 1, all modules off; running from flash ri dd 16 khz fbilp 3 77 ? a ?40 to 85 c t 16 khz fbelp 21 ? typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma)) 0 0.2 0.4 0.6 0.8 1 1.2 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.05 0.1 0.15 0.2 0.25 1234 v dd ? v oh (v) 25 c 85 c ?40 c 25 c, i oh = 2 ma 85 c, i oh = 2 ma ?40 c, i oh = 2 ma typical v dd ? v oh vs i oh at v dd = 3.0 v i oh (ma) 0 0.2 0.4 0.6 0.8 ?30 ?25 ?20 ?15 ?10 ?5 0 typical v dd ? v oh vs v dd at spec i oh v dd (v) v dd ? v oh (v) 0 0.1 0.2 0.3 0.4 1234 i oh = ?10 ma i oh = ?6 ma i oh = ?3 ma v dd ? v oh (v) 25 c 85 c ?40 c 25 c 85 c ?40 c
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 15 5 t run supply current lprs = 1, all modules off; running from ram ri dd 16 khz fbilp 3 77 ? a ?40 to 85 c t 16 khz fbelp 7.3 ? 6 t wait mode supply current fei mode, all modules off wi dd 10 mhz 3 570 ? a ?40 to 85 c t1 m h z 2 9 0 ? 7t wait mode supply current lprs = 1, all modules off wi dd 16 khz fbelp 31? a ?40 to 85 c 8 p stop2 mode supply current s2i dd ? 3 0.3 0.65 a ?40 to 25 c c ? 0.5 0.8 70 c p ? 1 2.5 85 c c? 2 0.25 0.50 ?40 to 25 c c ? 0.3 0.6 70 c c ? 0.7 2.0 85 c 9 p stop3 mode supply current no clocks active s3i dd ? 3 0.4 0.8 a ?40 to 25 c c ? 1.0 1.8 70 c p ? 3 6 85 c c? 2 0.35 0.60 ?40 to 25 c c ? 0.8 1.5 70 c c ? 2.5 5.5 85 c 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. table 9. stop mode adders num c parameter condition temperature units ?40 c 25 c 70 c 85 c 1 t lpo ? 50 75 100 150 na 2 t errefsten range = hgo = 0 1000 1000 1100 1500 na 3 t irefsten 1 ? 63707781 a 4 t rtc does not include clock source current 50 75 100 150 na 5tlvd 1 1 not available in stop2 mode. lvdse = 1 90 100 110 115 a 6tacmp 1 not using the bandgap (bgbe = 0) 18 20 22 23 a 7tadc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) 95 106 114 120 a table 8. supply current characteristics (continued) num c parameter symbol bus freq v dd (v) typical 1 max unit temp (c)
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 16 figure 11. typical run i dd for fbe and fei, i dd vs. v dd (adc off, all other modules enabled) tbd 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 1.8 2 2.2 2.4 2.6 2.8 3 vdd (v) idd (ma ) fei: 10 mhz fbelp: 10 mhz fei: 5 mhz fbelp: 5 mhz fei: 1 mhz fbelp: 1 mhz
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 17 3.8 external oscillator (xoscvlp) characteristics refer to figure 12 and figure 13 for crystal or resonator circuits. table 10. xoscvlp specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min. typical 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max. unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1), high gain (hgo = 1), fbelp mode high range (range = 1), low power (hgo = 0), fbelp mode f lo f hi f hi 32 1 1 ? ? ? 38.4 16 8 khz mhz mhz 2d load capacitors low range (range=0), low power (hgo = 0) other oscillator settings c 1, c 2 see note 2 see note 3 2 load capacitors ( c 1, c 2 ), feedback resistor ( r f ) and series resistor ( r s ) are incorporated internally when range = hgo = 0. 3 see crystal or resonator manufacturer?s recommendation. 3d feedback resistor low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range (range = 1, hgo = x) r f ? ? ? ? 10 1 ? ? ? m 4d series resistor ? low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range, low power (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? ? 100 0 0 0 0 ? ? ? 0 10 20 k 5c crystal start-up time 4 low range, low power low range, high gain high range, low power high range, high gain 4 proper pc board layout procedures must be followed to achieve specifications. t cstl t csth ? ? ? ? 600 400 5 15 ? ? ? ? ms 6d square wave input clock frequency (erefs = 0, erclken = 1) fee mode fbe or fbelp mode f extal 0.03125 0 ? ? 20 20 mhz mhz
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 18 figure 12. typical crystal or resonator circuit: high range and low range/high gain figure 13. typical crystal or resonator circuit: low range/low power 3.9 internal clock source (ics) characteristics table 11. ics frequency specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min. typical 1 max. unit 1p average internal reference frequency ? factory trimmed at v dd = 3.6 v and temperature = 25 c f int_t ? 32.768 ? khz 2p internal reference frequency ? user trimmed f int_ut 31.25 ? 39.06 khz 3t internal reference start-up time t irst ?510 s 4p dco output frequency range ? trimmed 2 low range (drs = 00) f dco_t 16 ? 20 mhz 5p dco output frequency 2 reference = 32768 hz and dmx32 = 1 f dco_dmx32 ? 19.92 ? mhz 6c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco xoscvlp extal xtal crystal or resonator r s c 2 r f c 1 xoscvlp extal xtal crystal or resonator
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 19 figure 14. deviation of dco output from trimmed frequency (20 mhz, 3.0 v) 7c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco 8c total deviation of dco outp ut from trimmed frequency 3 over full voltage and temperature range over fixed voltage and temperature range of 0 to 70 c f dco_t ? ?1.0 to 0.5 0.5 2 1 %f dco 10 c fll acquisition time 4 t acquire ?? 1ms 11 c long term jitter of dco output clock (averaged over 2-ms interval) 5 c jitter ?0.020.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 the resulting bus clock frequency should not exceed th e maximum specified bus clock frequency of the device. 3 this parameter is characterized and not tested on each device. 4 this specification applies to any time the fll reference so urce or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (f ei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 5 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 11. ics frequency specifications (temperature range = ?40 to 85 c ambient) (continued) num c characteristic symbol min. typical 1 max. unit tbd -2.00% -1.50% -1.00% -0.50% 0.00% 0.50% 1.00% -60 -40 -20 0 20 40 60 80 100 120 temperature deviation (%)
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 20 3.10 ac characteristics this section describes timing character istics for each peripheral system. 3.10.1 control timing figure 15. reset timing table 12. control timing num c rating symbol min typical 1 1 typical values are based on characterization data at v dd = 3.0 v, 25 c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus )f bus dc ? 10 mhz 2 d internal low power oscillator period t lpo 700 ? 1300 s 3d external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 t cyc ??ns 5d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns 6d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 3 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 ? ? s 7d irq pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. t ilih, t ihil 100 1.5 t cyc ? ? ? ? ns 8 d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 t cyc ? ? ? ? ns 9c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. t rise , t fall ? ? 16 23 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) 5 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 5 9 ? ? ns 10 c voltage regulator recovery time t vrr ?4? s t extrst reset pin
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 21 figure 16. irq /kbipx timing 3.10.2 tpm module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure 17. timer external clock figure 18. timer input capture pulse table 13. tpm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t ihil kbipx t ilih irq /kbipx t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 22 3.10.3 spi timing table 14 and figure 19 through figure 22 describe the timing requir ements for the spi system. table 14. spi timing no. c function symbol min max unit ?d operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz 1d spsck period master slave t spsck 2 4 2048 ? t cyc t cyc 2d enable lead time master slave t lead 1 / 2 1 ? ? t spsck t cyc 3d enable lag time master slave t lag 1 / 2 1 ? ? t spsck t cyc 4d clock (spsck) high or low time master slave t wspsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns 5d data setup time (inputs) master slave t su 15 15 ? ? ns ns 6d data hold time (inputs) master slave t hi 0 25 ? ? ns ns 7 d slave access time t a ?1t cyc 8 d slave miso disable time t dis ?1t cyc 9d data valid (after spsck edge) master slave t v ? ? 25 25 ns ns 10 d data hold time (outputs) master slave t ho 0 0 ? ? ns ns 11 d rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns 12 d fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 23 figure 19. spi master timing (cpha = 0) figure 20. spi master timing (cpha =1) spsck (output) spsck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 9 10 11 12 4 9 spsck (output) spsck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in master msb out (2) master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss (1) (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 24 figure 21. spi slave timing (cpha = 0) figure 22. spi slave timing (cpha = 1) 3.11 analog comparator (acmp) electricals table 15. analog comparator electrical specifications c characteristic symbol min typical max unit d supply voltage v dd 1.8 ? 3.6 v p supply current (active) i ddac ?2035 a spsck (input) spsck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 spsck (input) spsck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 25 3.12 adc characteristics d analog input voltage v ain v ss ? 0.3 ? v dd v p analog input offset voltage v aio ?2040mv c analog comparator hysteresis v h 3.0 9.0 15.0 mv p analog input leakage current i alkg ??1 .0 a c analog comparator initialization delay t ainit ??1 .0 s table 16. 12-bit adc operating conditions characteristic conditions symb min typical 1 1 typical values assume v dda = 3.0 v, temp = 25 c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply voltage absolute v dda 1.8 ? 3.6 v ? delta to v dd (v dd ? v dda ) 2 2 dc potential difference. v dda ?100 0 100 mv ? ground voltage delta to v ss (v ss ? v ssa ) 2 v ssa ?100 0 100 mv ? input voltage ? v adin v refl ?v refh v? input capacitance ?c adin ?4.55.5pf ? input resistance ?r adin ?5 7k ? analog source resistance 12-bit mode f adck > 4 mhz f adck < 4 mhz r as ? ? ? ? 2 5 k external to mcu 10-bit mode f adck > 4 mhz f adck < 4 mhz ? ? ? ? 5 10 8-bit mode (all valid f adck )??1 0 adc conversion clock freq. high speed (adlpc = 0) f adck 0.4 ? 8.0 mhz ? low power (adlpc = 1) 0.4 ? 4.0 table 15. analog comparator electrical specifications (continued) c characteristic symbol min typical max unit
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 26 figure 23. adc input impedance equivalency diagram table 17. adc characteristics (v refh = v dda , v refl = v ssa ) c characteristic conditions symbol min typ 1 max unit comment t supply current adlpc = 1 adlsmp = 1 adco = 1 i dda ?120 ? a t supply current adlpc = 1 adlsmp = 0 adco = 1 i dda ?202 ? a t supply current adlpc = 0 adlsmp = 1 adco = 1 i dda ?288 ? a p supply current adlpc = 0 adlsmp = 0 adco = 1 i dda ? 0.532 1 ma p adc asynchronous clock source high speed (adlpc = 0) f adack 23.3 5 mhz t adack = 1/f adack low power (adlpc = 1) 1.25 2 3.3 + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 27 p conversion time (including sample time) short sample (adlsmp = 0) t adc ?20 ? adck cycles see qe8 reference manual for conversion time variances long sample (adlsmp = 1) ? 40 ? p sample time short sample (adlsmp = 0) t ads ?3.5 ? adck cycles long sample (adlsmp = 1) ? 23.5 ? d temp sensor slope ?40 c? 25 c m ? 1.646 ? mv/ c 25 c? 85 c ? 1.769 ? d temp sensor voltage 25 cv temp25 ? 701.2 ? mv characteristics for devices with dedicated an alog supply (28- and 32-pin packages only) t to t a l unadjusted error 12-bit mode, 3.6> v dda > 2.7 e tue ? ?1 to 3 ?2.5 to 5.5 lsb 2 includes quantization t 12-bit mode, 2.7> v dda > 1.8v ? ?1 to 3 ?3.0 to 6.5 p 10-bit mode ? 1 2.5 p 8-bit mode ? 0.5 1.0 t differential non-linearity 12-bit mode dnl ? 1.0 ?1.5 to 2.0 lsb 2 p 10-bit mode 3 ? 0.5 1.0 p 8-bit mode 3 ? 0.3 0.5 t integral non-linearity 12-bit mode inl ? 1.5 ?2.5 to 2.75 lsb 2 t 10-bit mode ? 0.5 1.0 t 8-bit mode ? 0.3 0.5 t zero-scale error 12-bit mode e zs ? 1.5 2.5 lsb 2 v adin = v ssa p 10-bit mode ? 0.5 1.5 p 8-bit mode ? 0.5 0.5 t full-scale error 12-bit mode e fs ? 1.0 ?3.5 to 1.0 lsb 2 v adin = v dda p 10-bit mode ? 0.5 1 p 8-bit mode ? 0.5 0.5 d quantization error 12-bit mode e q ? ?1 to 0 ? lsb 2 10-bit mode ? ? 0.5 8-bit mode ? ? 0.5 table 17. adc characteristics (v refh = v dda , v refl = v ssa ) (continued) c characteristic conditions symbol min typ 1 max unit comment
mc9s08qe8 series data sheet, rev. 7 electrical characteristics freescale semiconductor 28 d input leakage error 12-bit mode e il ? 2? lsb 2 pad leakage 4 * r as 10-bit mode ? 0.2 4 8-bit mode ? 0.1 1.2 characteristics for devices with shared supply (16- and 20-pin packages only) t to t a l unadjusted error 12-bit mode e tue not recommended usage lsb 2 includes quantization p 10-bit mode ? 1.5 3.5 p 8-bit mode ? 0.7 1.5 t differential non-linearity 12-bit mode dnl not recommended usage lsb 2 p 10-bit mode 3 ? 0.5 1.0 p 8-bit mode 3 ? 0.3 0.5 t integral non-linearity 12-bit mode inl not recommended usage lsb 2 t 10-bit mode ? 0.5 1.0 t 8-bit mode ? 0.3 0.5 t zero-scale error 12-bit mode e zs not recommended usage lsb 2 v adin = v ssa p 10-bit mode ? 1.5 2.1 p 8-bit mode ? 0.5 0.7 t full-scale error 12-bit mode e fs not recommended usage lsb 2 v adin = v dda p 10-bit mode ? 1 1.5 p 8-bit mode ? 0.5 0.5 d quantization error 12-bit mode e q not recommended usage lsb 2 10-bit mode ? ? 0.5 8-bit mode ? ? 0.5 d input leakage error 12-bit mode e il not recommended usage lsb 2 pad leakage 4 * r as 10-bit mode ? 0.2 4 8-bit mode ? 0.1 1.2 1 typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwis e stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh ? v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 based on input pad leakage current. refer to pad electricals. table 17. adc characteristics (v refh = v dda , v refl = v ssa ) (continued) c characteristic conditions symbol min typ 1 max unit comment
electrical characteristics mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 29 3.13 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information about progra m/erase operations, see the memory section. 3.14 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and char acteristics of external components as well as mcu software operation all pl ay a significant role in emc performance. the system designer should consult freescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifi cally targeted at optimizing emc performance. table 18. flash characteristics c characteristic symbol min typical max unit d supply voltage for program/erase ?40 c to 85 cv prog/erase 1.8 ? 3.6 v d supply voltage for read operation v read 1.8 ? 3.6 v d internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 ? 200 khz d internal fclk period (1/fclk) t fcyc 5?6 . 6 7 s p byte program time (random location) 2 t prog 9t fcyc p byte program time (burst mode) 2 t burst 4t fcyc p page erase time 2 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. t page 4000 t fcyc p mass erase time 2 t mass 20,000 t fcyc byte program current 3 3 the program and erase currents are additional to the standard run i dd . these values are measured at room temperatures with v dd = 3.0 v, bus frequency = 4.0 mhz. ri ddbp ?4?m a page erase current 3 ri ddpe ?6?m a c program/erase endurance 4 t l to t h = ?40 c to 85 c t = 25 c 4 typical endurance for flash was evaluated for this product family on th e 9s12dx64. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 10,000 ? 100,000 ? ? cycles c data retention 5 5 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional informatio n on how freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. t d_ret 15 100 ? years
mc9s08qe8 series data sheet, rev. 7 ordering information freescale semiconductor 30 3.14.1 conducted transient susceptibility microcontroller transient conducted su sceptibility is measured in accord ance with an internal freescale test method. the measurement is performed with the microcontroller inst alled on a custom emc evaluation board and running specialize d emc test software designed in compliance with the test method. the conducted susceptibility is determined by injecti ng the transient susceptibility signal on each pin of the microcontroller. the transient waveform and injection methodology is based on iec 61000-4-4 (eft/b). the transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reporte d levels unless otherwise i ndicated by footnotes below table 19 . the susceptibility performance classification is described in table 20 . 4 ordering information this section contains ordering inform ation for the device numbering system. example of the device numbering system: table 19. conducted susceptibility, eft/b parameter symbol conditions f osc /f bus result amplitude 1 (min) 1 data based on qualification test re sults. not tested in production. unit conducted susceptibility, electrical fast transient/burst (eft/b) v cs_eft v dd = 3.3 v t a = 25 o c package type 32-pin lqfp 8 mhz crystal 8 mhz bus a2 . 3 kv b4 . 0 c> 4 . 0 d> 4 . 0 table 20. susceptibility performance classification result performance criteria a no failure the mcu performs as designed during and after exposure. b self-recovering failure the mcu does not perform as designed during exposure. the mcu returns automatically to normal operation after exposure is removed. c soft failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the reset pin is asserted. d hard failure the mcu does not perform as designed during exposure. the mcu does not return to normal operation until exposure is removed and the power to the mcu is cycled. e damage the mcu does not perform as designed dur ing and after exposure. the mcu cannot be returned to proper operation due to physical damage or other permanent performance degradation.
package information mc9s08qe8 series data sheet, rev. 7 freescale semiconductor 31 5 package information 5.1 mechanical drawings the following pages are me chanical drawings for th e packages described in table 21 . table 21. package descriptions pin count package type abbreviation designator case no. document no. 32 low quad flat package lqfp lc 873a 98ash70029a 28 small outline integrated circuit soic wl 751f 98asb42345b 20 small outline integrated circuit soic wj 751d 98asb42343b 16 plastic dual in-line package pdip pg 648 98asb42431b 16 thin shrink small outline package tssop tg 948f 98ash70247a mc temperature range family memory status core (c = ?40 c to 85 c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see ta b l e 2 1 ) approximate flash size in kbytes qe 8c

how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 200 7 -2009. all rights reserved. mc9s08qe8 rev. 7 4/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical ex perts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part.

▲Up To Search▲

Price & Availability of MC9S08QE4

	To Download MC9S08QE4 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .